Interconnection techniques are used in semiconductor processing to electrically interconnect devices over a semiconductor wafer. Historically in the semiconductor industry, subtractive metal etches or lift-off techniques have been employed as the main metal-patterning techniques. Metal etching usually involves the deposition of a conductive layer of material over the surface of the semiconductor substrate. The conductive material is then patterned and etched, whereby the conductive material is removed (i.e., subtracted) from the desired locations, leaving behind conductive interconnect lines. However, problems associated with this interconnect processing method include: increased process complexity; increased process steps due to preventing and/or removing corrosion of the conductive lines; lack of cost efficiency; resist burn and resist time criticality; etc. As such, increasing the density, performance, and fabrication parameters associated with semiconductor metallization have led to new approaches toward interconnect fabrication.
Damascene and dual damascene processes are examples of currently employed semiconductor processing methods that are used to form conductive lines and conductive contacts. The damascene technique is an interconnection fabrication process in which trenches or other recesses are formed in an insulation or dielectric layer of a semiconductor device. These trenches are then filled with a metal or other conductive material to form conductive structures. The dual damascene process is a multilevel interconnection fabrication process in which contact openings are also formed in an insulation or dielectric layer of a semiconductor device. The trenches and the contact openings are then concurrently filled with a conductive material to thereby create both wiring lines, or conductive traces or “runners,” and contact openings at the same time. See, for example, Kaanta et al., “Dual Damascene: A ULSI Wiring Technology,” VMIC, IEEE, June 11-12, 1991, pages 144-152; Licata et al., “Dual Damascene AI Wiring for 256M DRAM,” in Proceedings of VLSI Multilevel Interconnection Conference, June 27-29, 1995, pages 596-602; and U.S. Pat. Nos. 5,595,937; 5,598,027; 5,635,432; and 5,612,254. Since the damascene process provides wire patterning by dielectric etching, rather than metal etching, damascene processes facilitate the use of previously unusable metals for wiring lines, in particular copper, to be reconsidered. Utilizing copper may be preferred to conventionally used aluminum in many cases since copper includes a lower resistivity and potentially better reliability in terms of electromigration resistance than that of aluminum. Further, not only does the damascene process limit the number of required process steps in not having to prevent and/or remove corrosion to the wiring lines, but it is also much easier and less time consuming to pattern dielectric material than patterning a metal or conductive material.
The use of self-aligned contact etch techniques to form interconnects in semiconductor device structures is also known. An example of a method for forming a self-aligned contact is found in U.S. Pat. No. 5,728,595 (hereinafter the “'595 patent”) to Fukase. In the '595 patent, gate stacks are fabricated by conventional, non-damascene techniques on top of an active surface of a semiconductor substrate, then protected by side wall spacers and a cap. The gate stacks are then laterally surrounded with an insulation layer. A self-aligned contact opening is formed between adjacent gate stacks by etching silicon oxide side walls to form a self-aligned opening between the two gate stacks and, then, filling the self-aligned opening with a conductive material, such as polycrystalline silicon. The self-aligned contact is advantageous because it minimizes a mask alignment margin when aligning the mask preparatory to forming a contact since the contact side wall is an already fixed semiconductor element structure. In the '595 patent, the wiring lines are provided using the conventional subtractive metal etch techniques of applying a layer of conductive material and, then, removing selected portions of the conductive material to form the wiring lines. As a result, the device in the '595 patent includes the disadvantages of conventional, non-damascene wiring line fabrication processes, as previously set forth.
Thus, it would be advantageous to develop a technique and device that utilizes the advantages of both damascene conductive lines and a self-aligned contact, in which the steps to manufacture the product are reduced and the conductive lines and self-aligned contacts maintain their integrity.